Technical Program

Access the Virtual ETS Conference System here.

Synchronous Plenary Sessions

(60-minute live video sessions)

Moderators: Artur JUTMAN - Testonica, EE and Jaan RAIK - Tallinn UT, EE

May 25	Opening - Welcome to Virtual ETS 2020
^14:00CEST	Artur JUTMAN (Testonica), Jaan RAIK (Tallinn UT), Görschwin FEY (TU Hamburg), Maksim JENIHHIN (Tallinn UT), Sybille HELLEBRAND (Uni. Paderborn), Matteo SONZA REORDA (POLITO)
Jun 01	Closing - Conclusions of ETS 2020
^18:00CEST	Artur JUTMAN (Testonica), Jaan RAIK (Tallinn UT), Görschwin FEY (TU Hamburg), Maksim JENIHHIN (Tallinn UT)

Keynotes

(45-minute live and pre-recorded video presentations)

Moderators: Goerschwin FEY - TU Hamburg, DE and Maksim JENIHHIN - Tallinn UT, EE

May 25	Resilience of AI-driven Applications
^15:00CEST	Ravishankar K. IYER (Urbana Champaign, USA)
May 26	Safety-Critical Applications: An EDA perspective
	Alessandra NARDI (Cadence, USA)

Embedded Tutorials

(60-minute video presentations)

Moderators: Lorena ANGHEL - TIMA, FR and Gildas LEGER - IMSE-CNM, ES

May 27	Analog Fault Simulation - a Hot Topic!
(103)	Stephen SUNTER (Mentor, A Siemens Business)
	^{Keywords: Analog defect simulation, fault modeling}
May 28	Device-Aware Test for Emerging Memories: Enabling your test program for DPPB level
(100)	Lizhou WU, Moritz FIEBACK, Mottaqiallah TAOUIL, Said Hamdioui, Said HAMDIOUI (Delft University of Technology)
	^{Keywords: Device-Aware Test, STT-MRAM testing, RRAM testing, Defect modeling, Fault Modeling, Test generation}
May 29	Design, Verification, Test and In-Field Implications of Approximate Computing Systems
(105)	Alberto BOSIO (Ecole Centrale de Lyon), Stefano DI CARLO (Politecnico di Torino), Patrick GIRARD (LIRMM), Ernesto SANCHEZ, Alessandro Savino (Politecnico di Torino), Lukas Sekanina (Brno University of Technology), Marcello Traiola (Ecole Centrale de Lyon), Zdenek VASICEK (Brno University of Technology), Arnaud VIRAZEL (LIRMM)
	^{Keywords: Approximate computing, energy efficiency, testing, verification, design space exploration, reliability}

Long Scientific Papers

(30-minute video presentations)

Session L1 - Test infrastructure and embedded test

Moderator: Martin KEIM - Mentor, A Siemens Business, US

Paper ID
6	Test Sequence-Optimized BIST for Automotive Applications
	Bartosz KACZMAREK, Grzegorz MRUGALSKI, Nilanjan MUKHERJEE, Janusz RAJSKI, Łukasz RYBAK (Mentor, A Siemens Business), Jerzy TYSZER (Poznan University of Technology)
	^{Keywords: embedded-test, logic built-in self-test, LFSR reseeding, scan-based testing, test application time}
41	Dynamic Authentication-Based Secure Access to Test Infrastructure
	Michele PORTOLAN, Vincent REYNAUD (Grenoble-INP), Paolo MAISTRI (CNRS), Regis LEVEUGLE (Grenoble INP)
	^{Keywords: Reconfigurable Scan Networks, Secure Access, Authentication, Automated Test Environments, IEEE 1687}
70	Minimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks
	Pascal RAIOLA, Tobias PAXIAN, Bernd BECKER (University of Freiburg)
	^{Keywords: Reconfigurable Scan Network, Hardware Security, Data Dependency, IEEE Std 1687, Insecure Data Flow}

Session L2 - Testing of emerging memory-based architectures

Moderator: Elena Ioana VATAJELU - TIMA, FR

76	Testing Scouting Logic-Based Computation-in-Memory Architectures
	Moritz FIEBACK, Surya NAGARAJAN, Rajendra BISHNOI (Delft University of Technology), Mehdi TAHOORI (Karlsruhe Institute of Technology), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology)
	^{Keywords: test, computation-in-memory (CIM), in-memory computing, emerging memories, RRAM}
49	Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory
	Sarath MOHANACHANDRAN NAIR, Christopher MÜNCH, Mehdi TAHOORI (Karlsruhe Institute of Technology)
	^{Keywords: STT-MRAM, In-memory computing, Defect modeling}
78	MBIST Support for Reliable eMRAM Sensing
	Jongsin YUN, Benoit NADEAU-DOSTIE, Martin KEIM (Mentor, A Siemens Business), Cyrille DRAY, Mehdi BOUJAMAA (ARM)
	^{Keywords: eMRAM, yield, trim, reference, read operation}

Session L3 - ATPG and cell-aware characterization

Moderator: Maria MICHAEL - Uni. Cyprus, CY

75	Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching Weakest Faults
	Min-Chun HU (National Tsing-Hua University), Zhan GAO (IMEC), Santosh MALAGI, Joe SWENTON (Cadence Design Systems), Jos HUISKEN, Kees GOOSSENS (Eindhoven University of Technology), Cheng-Wen WU (National Tsing Hua University), Erik Jan MARINISSEN (IMEC)
	^{Keywords: cell-aware test, weak fault, hard fault, defect characterization, ATPG}
66	Variation-Aware Defect Characterization at Cell Level
	Zahra Paria NAJAFI-HAGHI, Marzieh HASHEMIPOUR NAZARI, Hans-Joachim WUNDERLICH (Stuttgart University)
	^{Keywords: Small delay faults, variations, reliability, defect modeling, statistical learning}
92	Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model
	Ching-Yuan CHEN (Duke University), Ching-Hung CHENG, Jiun-Lang HUANG (National Taiwan University), Krishnendu CHAKRABARTY (Duke University)
	^{Keywords: functional-like, automatic test pattern generation, full-scan}

Session L4 - Fault screening and protection methods

Moderator: Regis LEVEUGLE - Grenoble INP, FR

91	Nonlinear Codes for Control Flow Checking
	Giorgio DI NATALE (TIMA), Osnat KEREN (Bar-Ilan University)
	^{Keywords: CFC}
19	QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead Reduction
	Bastien DEVEAUTOUR, Marcello TRAIOLA, Arnaud VIRAZEL, Patrick GIRARD (LIRMM)
	^{Keywords: Combinational circuits; fault tolerance; error correction; triple modular redundancy; approximate computing}
43	Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs
	Felipe AUGUSTO DA SILVA, Ahmet Cagri BAGBABA (Cadence Design Systems GmbH), Sandro SARTONI, Riccardo CANTORO, Matteo SONZA REORDA (Politecnico di Torino), Said HAMDIOUI (Delft University of Technology), Christian SAUER (Cadence Design Systems GmbH)
	^{Keywords: ISO26262; Safe Faults; Fault Injection; Formal Methods; Simulation; Functional Safety; Verification}

Session L5 - Technology

Moderator: Erik Jan MARINISSEN - IMEC, BE

71	Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios
	Michele STUCCHI, Ferenc FODOR, Erik Jan MARINISSEN (IMEC)
	^{Keywords: resistance, vertical interconnect, cross-bridge Kelvin resistor, current and voltage distributions}
35	A Built-In Self-Test Method For MEMS Piezoresistive Sensor
	Manhong ZHU, Jia LI, Weibing WANG, Dapeng CHEN (Institute of Microelectronics, Chinese Academy of Sciences)
	^{Keywords: MEMS; piezoresistive sensor; built-in self-test; electric excitation}
63	Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications
	Daniel OLIVEIRA (UFPR), Sean BLANCHARD, Nathan DEBARDELEBEN (LANL), Fernando SANTOS, Gabriel DAVILA, Philippe NAVAUX (UFRGS), Cazzaniga CARLO (Rutherford Appleton Laboratory-ISIS), Christopher FROST (STFC), Robert C. BAUMANN, Paolo RECH (LANL)
	^{Keywords: Radiation test, Thermal Neutrons, Reliability}

Session L6 - Statistical approaches

Moderator: Alberto BOSIO - INL, FR

13	Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing
	Anthony COYETTE, Wim DOBBELAERE, Ronny VANHOOREN (ON Semiconductor), Nektar XAMA (KULeuven), Jhon GOMEZ, Georges GIELEN (KU Leuven)
	^{Keywords: Latent defects, outlier detection, analog and mixed-signal testing, integrated circuits, DPAT, visualization}
29	PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques
	Katherine Shu-Min LI (National Sun Yat-sen University), Peter Yi-Yu LIAO, Leon CHOU, Ken Chau-Cheung CHENG, Andrew Yi-Ann HUANG (NXP Semiconductor Taiwan Ltd.), Sying-Jyan WANG, Gus Chang-Hung HAN (National Chung-Hsing University)
	^{Keywords: wafermap, defect pattern, yield learning, clustering, machine learning}
46	Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics
	Nektar XAMA, Jakob RAYMAEKERS (KU Leuven), Martin ANDRAUD (Aalto university), Jhon GOMEZ (KU Leuven), Wim DOBBELAERE, Ronny VANHOOREN, Anthony COYETTE (ON Semiconductor), Georges GIELEN (KU Leuven)
	^{Keywords: analog and mixed-signal test, test escape screening, multivariate statistics, latent defect testing}

Session L7 - Hardware Security

Moderator: Ilia POLIAN - Uni. Stuttgart, DE

25	The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs
	David KNICHEL (Ruhr-University Bochum), Thorben MOOS (Ruhr-University Bochum, Horst Görtz Institute for IT Security), Amir MORADI (Ruhr-University Bochum)
	^{Keywords: hardware Trojan, ASIC, side-channel analysis, time-to-digital converter}
72	Modeling Static Noise Margin for FinFET based SRAM PUFs
	Shayesteh MASOUMIAN, Georgios SELIMIS, Roel MAES, Geert-Jan SCHRIJEN (Intrinsic ID), Said HAMDIOUI, Mottaqiallah TAOUIL (Delft University of Technology)
	^{Keywords: SRAM PUF, FinFET, Static noise margin, process variation, temperature}
58	Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism
	Mohamed ELSHAMY (Sorbonne Univ., CNRS, LIP6), Giorgio DI NATALE (TIMA), Antonios PAVLIDIS (Sorbonne Univ., CNRS, LIP6), Marie-Minerve LOUERAT (Sorbonne Univ., CNRS), Haralampos STRATIGOPOULOS (Sorbonne Univ., CNRS, LIP6)
	^{Keywords: Hardware Security, Hardware Trojans, Analog and Mixed-Signal Circuits, Test Access Mechanism}

Session L8 - Built-in monitoring

Moderator: Massimo VIOLANTE - POLITO, IT

84	LiD-CAT: A Lightweight Detector for Cache ATtacks
	Cezar Rodolfo WEDIG REINBRECHT, Said HAMDIOUI, Mottaqiallah TAOUIL (Delft University of Technology), Behrad NIAZMAND, Tara GHASEMPOURI, Jaan RAIK (Tallinn University of Technology), Johanna SEPULVEDA (Airbus Defence and Space)
	^{Keywords: cache attacks, security properties, lightweight detector}
51	Built-In Predictors for Dynamic Crosstalk Avoidance
	Rezgar SADEGHI, Zainalabedin NAVABI (University of Tehran)
	^{Keywords: Crosstalk Fault, Interconnect, Communication Bus, Crosstalk Prediction, Crosstalk Model}
60	A New Monitor Insertion Algorithm for Intermittent Fault Detection
	Hassan EBRAHIMI, Hans KERKHOFF (University of Twente)
	^{Keywords: Reliability; No Faults Found, Intermittent Resistive Faults, Intermittent Fault Detection}

Short Scientific Papers

(15-minute video presentations or posters)

Session S1 - Solutions towards the technology layer

Moderator: Haralampos STRATIGOPOULOS – CNRS/LIP6, FR

65	On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter
	Renato FEITOZA, Manuel BARRAGAN (TIMA Laboratory), Antonio GINES (IMSE-CNM (CSIC, Universidad de Sevilla)), Salvador MIR (TIMA Laboratory)
	^{Keywords: ADC BIST; Static linearity test; Reduced-code test}
79	Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators
	Mehmet INCE, Sule OZEV (Arizona State University)
	^{Keywords: Built-in Self-Test, LDO}
69	Monitoring of BTI and HCI Aging in SRAM Decoders
	Helen-Maria DOUNAVI, Yiorgos TSIATOUHAS (Univ. of Ioannina)
	^{Keywords: BTI, HCI, aging monitoring, SRAM Decoders, transistor aging, reliability, failure prediction}
86	G-PUF: An Intrinsic PUF Based on GPU Error Signatures
	Bruno FORLIN, Ronaldo HUSEMANN, Luigi CARRO (UFRGS), Cezar Rodolfo WEDIG REINBRECHT, Said HAMDIOUI, Mottaqiallah TAOUIL (Delft University of Technology)
	^{Keywords: G-PUF, Physically Unclonable Functions, GPU, Security, Intrinsic PUF}
26	A SIFT-based Waveform Clustering Method for aiding analog/mixed-signal IC Verification
	Andrei GAITA, Georgian NICOLAE (Universitatea Politehnica din Bucuresti), Emilian Constantin DAVID (Infineon Technologies Bucharest, Romania), Andi BUZO (Infineon), Georg PELZ (Infineon Technologies, Neubiberg, Germany)
	^{Keywords: SIFT, wavelet, DCT, K-means}
36	Learning-Based Cell-Aware Defect Diagnosis of Customer Returns
	Safa MHAMDI, Patrick GIRARD, ARNAUD VIRAZEL (LIRMM), ALBERTO BOSIO (Lyon Institute of Nanotechnology), Aymen LADHAR (STM)
	^{Keywords: Diagnosis, Customer Returns, Machine Learning}

Session S2 - Solutions towards the system layer

Moderator: Christoph SCHOLL - Uni. Freiburg, DE

89	Anomaly Detection in Embedded Systems Using Power and Memory Side Channels
	Jiho PARK, Virinchi Roy SURABHI, Prashanth KRISHNAMURTHY, Siddharth GARG, Ramesh KARRI, Farshad KHORRAMI (NYU)
	^{Keywords: Anomaly detection, cyber security, power consumption, memory access, one-class support vector machine}
31	Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation
	Jo LAUFENBERG, Thomas KROPF, Oliver BRINGMANN (University of Tuebingen)
	^{Keywords: fault injection, graph, robustness, simulation, virtual prototype}
11	Efficient Prognostication of Pattern Count with Different Input Compression Ratios
	Fong-Jyun TSAI, Chong-Siao YE (National Cheng Kung University), Yu HUANG (Mentor, A Siemens Business), Kuen Jong LEE (National Cheng Kung Univ), Wu-Tung CHENG (Mentor, A Siemens Business), Sudhakar REDDY (University of Iowa), Mark KASSAB , Janusz RAJSKI (Mentor, A Siemens Business)
	^{Keywords: design for testability, embedded-test, scan-based designs, runtime reduction}
57	Failure and Attack Detection by Digital Sensors
	Md Toufiq Hasan ANIK, Rachit SAINI (University of Maryland Baltimore County), Jean-Luc DANGER (Télécom Paris, Institut Polytechnique de Paris), Sylvain GUILLEY (Télécom ParisTech, Université Paris-Saclay), Naghmeh KARIMI (University of Maryland Baltimore County)
	^{Keywords: Digital Sensors, Failure Detection, Attack Detection, Security, Aging}
32	Detection of Rowhammer Attacks in SoCs with FPGAs
	Rana ELNAGGAR, Siyuan CHEN (Duke University), Peilin SONG (IBM Corp.), Krishnendu CHAKRABARTY (Duke University)
	^{Keywords: FPGA-SoC, Rowhammer, security, FPGA-to-microprocessor SDRAM}
14	IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks
	Erik LARSSON, Zehang XIANG, Prathamesh MURALI (Lund University)
	^{Keywords: IEEE Std. P1687.1, IEEE Std. 1687, test, localization, repair, access control}

Special Sessions

(sessions of 3 * 30-minute video presentations)

Moderators: Xinli GU - Futurewei, US and Bernd BECKER - Uni. Freiburg, DE

108	Design Obfuscation versus Test
	Farimah FARAHMANDI (University of Florida), Ozgur SINANOGLU (NYU Abu Dhabi), Ronald BLANTON (Carnegie Mellon University), Samuel PAGLIARINI (TalTech)
	^{Keywords: hardware security, ATPG, sequential ATPG, high level synthesis, design obfuscation}
	- Design Obfuscation versus Test Ronald (Shawn) BLANTON (Carnegie Mellon University) - Logic Locking: Metrics, Secure Implementation and Connections to VLSI Test Concepts Ozgur SINANOGLU (NYU Abu Dhabi) - Secure High-level Synthesis for Hardware Obfuscation Farimah FARAHMANDI (University of Florida)
114	Linking Chip, Board, and System Test via Standards
	Michele PORTOLAN (Grenoble-INP), Jeff REARICK (AMD), Martin KEIM (Mentor, A Siemens Business)
	^{Keywords: IC test, board test, system test, 1687, 1687.1, 2654, IJTAG, test standards}
	(Comment: to be watched in the same sequence) - A Path Toward Realizing the Vision of System-Board-Chip Test Synergy Jeff REARICK (AMD) - Making Embedded Chip Test Features and Chip Tests Usable Through Functional Martin KEIM (Mentor, A Siemens Business) - Re-using Test Assets in a System Context Through Interface Transformations Michele PORTOLAN (Grenoble-INP)
110	PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community
	David HELY (Grenoble INP), Giorgio DI NATALE (TIMA)
	Keywords: hardware security; Test; Physical Unclonable Function; lifecycle
	- PUFs Introduction and Standardization Process Sylvain GUILLEY (Télécom Paris) - Leveraging Secure IC Testing for Secure PUF Enrollment David HELY (Grenoble INP), Bertrand CAMBOU (Northern Arizona University) - Deep Learning Techniques for Challenge/Response Pair Database Management During the Life Cycle Amir ALIPOUR, David HELY (Universite Grenoble Alpes), Giorgio DI NATALE (TIMA), Vincent BEROULLE (Universite Grenoble Alpes) - On line Test to check the PUF Integrity and Security in Mission Mode Jean-Luc DANGER, Sylvain GUILLEY (Télécom Paris), Naghmeh KARIMI (University of Maryland Baltimore County)
116*	Reliable and Energy-efficient Artificial Intelligence for Real-Time Systems
	Saibal MUKHOPADHYAY (Georgia Institute of Technology), Kaushik ROY (Purdue University), Priyadarshini PANDA (Yale University), Amit TRIVEDI (University of Illionois)
	^{Keywords: Reliable, efficient, artificial intelligence}
	- Energy-efficiency and robustness through spiking neural networks Kaushik ROY (Purdue University) - On Adversarial susceptibility and Defense Of Neural Networks Priyadarshini PANDA (Yale University) - R3AI: Hardware Design Principles for Real-time, Resource-Savvy, and Risk-aware AI Amit TRIVEDI (University of Illionois) - Reliable Intelligence in Unreliable Environment Saibal MUKHOPADHYAY (Georgia Institute of Technology)

Informal Case Studies and Hot Topics

(15-minute video presentations)

Moderators: Stephan EGGERSGLUESS - Mentor, A Siemens Business, DE and Mihalis PSARAKIS - Uni. Piraeus, GR and Rene KRENZ-BAATH - HSHL, DE

83	Enabling DFT and Fast Silicon Bring-up for Massive AI Chip – Case Study
	Hui King LAU, Jon FERGUSON, Evan GRIFFITHS (Graphcore), Rahul SINGHAL, Lee HARRISON (Mentor, A Siemens Business)
	^{Keywords: DFT, Hierarchical ATPG, AI, artificial intelligence, LBIST, IJTAG, Silicon bringup 1687}
82	IEEE 1687-Based Testing Methodology for AI SoC Integrating Embedded TAP and IEEE 1500 Interfaces
	Haiying MA, Ligang LU, Haitao QIAN, Jing HAN (Enflame Technology), Xin WEN, Fanjin MENG, Rahul SINGHAL, Martin KEIM, Yu HUANG, Wu YANG (Mentor, A Siemens Business)
	^{Keywords: IEEE 1687, IEEE 1500, IJTAG, eTAP, TAP, HBM, 2.5D, DFT, AI, DRAM}
48	Improving the Stuck-at fault coverage using Digital fault grading flow
	Rama KODAMANCHILI, Swathy SEN (Intel Technology India PVT LTD)
	^{Keywords: Fault grading, Scan, ATPG, HVM, gate-level, coverage, observation points, toggle simulation, Stuck-at fault}

PhD Forum